{"title":"时间冗余纠错加法器和乘法器","authors":"Y. Hsu, E. Swartzlander","doi":"10.1109/DFTVS.1992.224350","DOIUrl":null,"url":null,"abstract":"Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. The hardware overhead of time redundant error correcting adders and multipliers is much lower than that of hardware or information redundancy approaches. Hence they are useful in systems where hardware complexity is the primary concern.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"156 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"41","resultStr":"{\"title\":\"Time redundant error correcting adders and multipliers\",\"authors\":\"Y. Hsu, E. Swartzlander\",\"doi\":\"10.1109/DFTVS.1992.224350\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. The hardware overhead of time redundant error correcting adders and multipliers is much lower than that of hardware or information redundancy approaches. Hence they are useful in systems where hardware complexity is the primary concern.<<ETX>>\",\"PeriodicalId\":319218,\"journal\":{\"name\":\"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"156 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"41\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1992.224350\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1992.224350","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Time redundant error correcting adders and multipliers
Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. The hardware overhead of time redundant error correcting adders and multipliers is much lower than that of hardware or information redundancy approaches. Hence they are useful in systems where hardware complexity is the primary concern.<>
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