{"title":"由于TEOS/O/sub - 3/-氧化物中有水和ECR-SiO/sub - 2/的阻水作用，热载流子降解增强","authors":"N. Shimoyama, K. Machida, K. Murase, T. Tsuchiya","doi":"10.1109/VLSIT.1992.200665","DOIUrl":null,"url":null,"abstract":"The effect of water and/or silanols in TEOS/O/sub 3/-oxide on hot-carrier degradation is discussed. Hot-carrier degradation in MOSFETs is a serious problem as the thickness of the TEOS/O/sub 3/-oxide interlayer dielectric increases. This results mainly from enhanced hot-electron trapping and also from interface-trap generation, which are related to water and/or silanols in TEOS/O/sub 3/-oxide diffusing into the gate oxide. It is pointed out that by applying an ECR (electron cyclotron resonance) SiO/sub 2/ layer under the TEOS/O/sub 3/-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O/sub 3/-oxide layer.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"128 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Enhanced hot-carrier degradation due to water in TEOS/O/sub 3/-oxide and water blocking effect of ECR-SiO/sub 2/\",\"authors\":\"N. Shimoyama, K. Machida, K. Murase, T. Tsuchiya\",\"doi\":\"10.1109/VLSIT.1992.200665\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The effect of water and/or silanols in TEOS/O/sub 3/-oxide on hot-carrier degradation is discussed. Hot-carrier degradation in MOSFETs is a serious problem as the thickness of the TEOS/O/sub 3/-oxide interlayer dielectric increases. This results mainly from enhanced hot-electron trapping and also from interface-trap generation, which are related to water and/or silanols in TEOS/O/sub 3/-oxide diffusing into the gate oxide. It is pointed out that by applying an ECR (electron cyclotron resonance) SiO/sub 2/ layer under the TEOS/O/sub 3/-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O/sub 3/-oxide layer.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"128 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200665\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200665","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Enhanced hot-carrier degradation due to water in TEOS/O/sub 3/-oxide and water blocking effect of ECR-SiO/sub 2/
The effect of water and/or silanols in TEOS/O/sub 3/-oxide on hot-carrier degradation is discussed. Hot-carrier degradation in MOSFETs is a serious problem as the thickness of the TEOS/O/sub 3/-oxide interlayer dielectric increases. This results mainly from enhanced hot-electron trapping and also from interface-trap generation, which are related to water and/or silanols in TEOS/O/sub 3/-oxide diffusing into the gate oxide. It is pointed out that by applying an ECR (electron cyclotron resonance) SiO/sub 2/ layer under the TEOS/O/sub 3/-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O/sub 3/-oxide layer.<>
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