多千兆网络IPsec协议套件的FPGA实现

2017 International Conference on Systems, Signals and Image Processing (IWSSIP) Pub Date : 2017-05-01 DOI:10.1109/IWSSIP.2017.7965619

Mateusz Korona, K. Skowron, Mateusz Trzepinski, M. Rawski

{"title":"多千兆网络IPsec协议套件的FPGA实现","authors":"Mateusz Korona, K. Skowron, Mateusz Trzepinski, M. Rawski","doi":"10.1109/IWSSIP.2017.7965619","DOIUrl":null,"url":null,"abstract":"IPsec is a suite of protocols that adds security to communications at the IP level. However, the high computing power required by the IPsec algorithms limits network connection performance. The paper presents the hardware implementation of IPsec gateway in FPGA. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.","PeriodicalId":302860,"journal":{"name":"2017 International Conference on Systems, Signals and Image Processing (IWSSIP)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"FPGA implementation of IPsec protocol suite for multigigabit networks\",\"authors\":\"Mateusz Korona, K. Skowron, Mateusz Trzepinski, M. Rawski\",\"doi\":\"10.1109/IWSSIP.2017.7965619\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"IPsec is a suite of protocols that adds security to communications at the IP level. However, the high computing power required by the IPsec algorithms limits network connection performance. The paper presents the hardware implementation of IPsec gateway in FPGA. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.\",\"PeriodicalId\":302860,\"journal\":{\"name\":\"2017 International Conference on Systems, Signals and Image Processing (IWSSIP)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Conference on Systems, Signals and Image Processing (IWSSIP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSSIP.2017.7965619\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Systems, Signals and Image Processing (IWSSIP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSSIP.2017.7965619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 12

摘要

IPsec是一套为IP级别的通信增加安全性的协议。但是，IPsec算法对计算能力的要求很高，限制了网络连接性能。本文介绍了IPsec网关在FPGA中的硬件实现。该方案的效率允许在数据速率为几Gbit/s的网络中使用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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FPGA implementation of IPsec protocol suite for multigigabit networks

IPsec is a suite of protocols that adds security to communications at the IP level. However, the high computing power required by the IPsec algorithms limits network connection performance. The paper presents the hardware implementation of IPsec gateway in FPGA. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.

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2017 International Conference on Systems, Signals and Image Processing (IWSSIP)

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