T. Yonehara, Y. Kajiwara, D. Kato, K. Uesugi, T. Shimizu, Y. Nishida, H. Ono, A. Shindome, A. Mukai, A. Yoshioka, M. Kuraguchi
{"title":"通过控制SiO2栅极介质中的杂质密度改善GaN mosfet的正偏置温度不稳定性","authors":"T. Yonehara, Y. Kajiwara, D. Kato, K. Uesugi, T. Shimizu, Y. Nishida, H. Ono, A. Shindome, A. Mukai, A. Yoshioka, M. Kuraguchi","doi":"10.1109/IEDM.2017.8268490","DOIUrl":null,"url":null,"abstract":"Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"328 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Improvement of positive bias temperature instability characteristic in GaN MOSFETs by control of impurity density in SiO2 gate dielectric\",\"authors\":\"T. Yonehara, Y. Kajiwara, D. Kato, K. Uesugi, T. Shimizu, Y. Nishida, H. Ono, A. Shindome, A. Mukai, A. Yoshioka, M. Kuraguchi\",\"doi\":\"10.1109/IEDM.2017.8268490\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.\",\"PeriodicalId\":412333,\"journal\":{\"name\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"328 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2017.8268490\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268490","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improvement of positive bias temperature instability characteristic in GaN MOSFETs by control of impurity density in SiO2 gate dielectric
Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.