{"title":"设计高效细粒度信号处理器的快速周转系统","authors":"J. Beekman, R. Owens, M. J. Irwin","doi":"10.1109/HICSS.1989.47148","DOIUrl":null,"url":null,"abstract":"A CAD (computer-aided design tool set) designed for rapid prototyping of a specific class of high-performance signal processing architectures is presented. Efficient implementation of these architectures results in systems that are very fast (<35-ns clock cycle) and can be very small in size (<500 lambda by 500 lambda ). The system is composed of five software tools that have been designed to work together. The designer inputs an algorithmic description of the application architecture, and the design system outputs the layouts of the chip set for the application architecture. While many of these tools require a large amount of run time, they allow efficient automatic production of chip sets for applications that before could only be done by hand and therefore were virtually intractable problems.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A rapid turn-around system for designing efficient fine grained signal processors\",\"authors\":\"J. Beekman, R. Owens, M. J. Irwin\",\"doi\":\"10.1109/HICSS.1989.47148\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CAD (computer-aided design tool set) designed for rapid prototyping of a specific class of high-performance signal processing architectures is presented. Efficient implementation of these architectures results in systems that are very fast (<35-ns clock cycle) and can be very small in size (<500 lambda by 500 lambda ). The system is composed of five software tools that have been designed to work together. The designer inputs an algorithmic description of the application architecture, and the design system outputs the layouts of the chip set for the application architecture. While many of these tools require a large amount of run time, they allow efficient automatic production of chip sets for applications that before could only be done by hand and therefore were virtually intractable problems.<<ETX>>\",\"PeriodicalId\":300182,\"journal\":{\"name\":\"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-01-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HICSS.1989.47148\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HICSS.1989.47148","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A rapid turn-around system for designing efficient fine grained signal processors
A CAD (computer-aided design tool set) designed for rapid prototyping of a specific class of high-performance signal processing architectures is presented. Efficient implementation of these architectures results in systems that are very fast (<35-ns clock cycle) and can be very small in size (<500 lambda by 500 lambda ). The system is composed of five software tools that have been designed to work together. The designer inputs an algorithmic description of the application architecture, and the design system outputs the layouts of the chip set for the application architecture. While many of these tools require a large amount of run time, they allow efficient automatic production of chip sets for applications that before could only be done by hand and therefore were virtually intractable problems.<>