Narayanan Terizhandur Varadharajan, M. Ozen, Kazunari Koga, H. Mandavia
{"title":"为3D-IC封装架构实现更快的设计/性能决策","authors":"Narayanan Terizhandur Varadharajan, M. Ozen, Kazunari Koga, H. Mandavia","doi":"10.1109/SEMI-THERM.2017.7896910","DOIUrl":null,"url":null,"abstract":"Smaller footprints along with higher bandwidth needs and tightening power performance requirements are forcing the move towards 3D-IC package architectures. This is compounded by the fast pace of development in the mobile, automotive and internet-of-things (IoT) market segments. During the design process, engineers have to access many design and analysis tools, but most of the design flow is often unconnected and design data is exchanged manually. To meet aggressive schedule and market requirements, we aim to showcase a flow to tackle the problem with a native 3D hierarchical design approach incorporating IC-package co-design. Finally, we illustrate the benefits of using such an approach for solving the all-critical thermal “hotspot” issue in a 3D stacked IC design, as seen in the image below, facilitating a quick turnaround for design/performance decisions.","PeriodicalId":442782,"journal":{"name":"2017 33rd Thermal Measurement, Modeling & Management Symposium (SEMI-THERM)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Enabling faster design/performance decisions for 3D-IC package architectures\",\"authors\":\"Narayanan Terizhandur Varadharajan, M. Ozen, Kazunari Koga, H. Mandavia\",\"doi\":\"10.1109/SEMI-THERM.2017.7896910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Smaller footprints along with higher bandwidth needs and tightening power performance requirements are forcing the move towards 3D-IC package architectures. This is compounded by the fast pace of development in the mobile, automotive and internet-of-things (IoT) market segments. During the design process, engineers have to access many design and analysis tools, but most of the design flow is often unconnected and design data is exchanged manually. To meet aggressive schedule and market requirements, we aim to showcase a flow to tackle the problem with a native 3D hierarchical design approach incorporating IC-package co-design. Finally, we illustrate the benefits of using such an approach for solving the all-critical thermal “hotspot” issue in a 3D stacked IC design, as seen in the image below, facilitating a quick turnaround for design/performance decisions.\",\"PeriodicalId\":442782,\"journal\":{\"name\":\"2017 33rd Thermal Measurement, Modeling & Management Symposium (SEMI-THERM)\",\"volume\":\"161 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 33rd Thermal Measurement, Modeling & Management Symposium (SEMI-THERM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SEMI-THERM.2017.7896910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 33rd Thermal Measurement, Modeling & Management Symposium (SEMI-THERM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SEMI-THERM.2017.7896910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Enabling faster design/performance decisions for 3D-IC package architectures
Smaller footprints along with higher bandwidth needs and tightening power performance requirements are forcing the move towards 3D-IC package architectures. This is compounded by the fast pace of development in the mobile, automotive and internet-of-things (IoT) market segments. During the design process, engineers have to access many design and analysis tools, but most of the design flow is often unconnected and design data is exchanged manually. To meet aggressive schedule and market requirements, we aim to showcase a flow to tackle the problem with a native 3D hierarchical design approach incorporating IC-package co-design. Finally, we illustrate the benefits of using such an approach for solving the all-critical thermal “hotspot” issue in a 3D stacked IC design, as seen in the image below, facilitating a quick turnaround for design/performance decisions.