为3D-IC封装架构实现更快的设计/性能决策

Narayanan Terizhandur Varadharajan, M. Ozen, Kazunari Koga, H. Mandavia
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引用次数: 0

摘要

更小的尺寸、更高的带宽需求和更严格的功率性能要求正在推动3D-IC封装架构的发展。移动、汽车和物联网(IoT)细分市场的快速发展使这种情况更加复杂。在设计过程中,工程师必须访问许多设计和分析工具,但大多数设计流程通常是不连接的,设计数据是手动交换的。为了满足积极的进度和市场需求,我们的目标是展示一种流程,通过结合ic封装协同设计的本地3D分层设计方法来解决问题。最后,我们说明了使用这种方法解决3D堆叠IC设计中所有关键的热“热点”问题的好处,如下图所示,促进了设计/性能决策的快速周转。
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Enabling faster design/performance decisions for 3D-IC package architectures
Smaller footprints along with higher bandwidth needs and tightening power performance requirements are forcing the move towards 3D-IC package architectures. This is compounded by the fast pace of development in the mobile, automotive and internet-of-things (IoT) market segments. During the design process, engineers have to access many design and analysis tools, but most of the design flow is often unconnected and design data is exchanged manually. To meet aggressive schedule and market requirements, we aim to showcase a flow to tackle the problem with a native 3D hierarchical design approach incorporating IC-package co-design. Finally, we illustrate the benefits of using such an approach for solving the all-critical thermal “hotspot” issue in a 3D stacked IC design, as seen in the image below, facilitating a quick turnaround for design/performance decisions.
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