{"title":"温度对比较器偏置电压变化影响的测量","authors":"Yuma Iwata, T. Kitamura, Mahfuzul Islam","doi":"10.1109/ICMTS55420.2023.10094194","DOIUrl":null,"url":null,"abstract":"Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Measurement of Temperature Effect on Comparator Offset Voltage Variation\",\"authors\":\"Yuma Iwata, T. Kitamura, Mahfuzul Islam\",\"doi\":\"10.1109/ICMTS55420.2023.10094194\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.\",\"PeriodicalId\":275144,\"journal\":{\"name\":\"2023 35th International Conference on Microelectronic Test Structure (ICMTS)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-03-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 35th International Conference on Microelectronic Test Structure (ICMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS55420.2023.10094194\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS55420.2023.10094194","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Measurement of Temperature Effect on Comparator Offset Voltage Variation
Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.