3D集成电路测试调度与测试垫考虑

Ming-Hsuan Hsu, Chun-Hua Cheng, Shih-Hsu Huang
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引用次数: 1

摘要

随着设计复杂性的增加,三维(3D)集成电路(IC)设计已成为一种行业趋势。然而,3D集成电路的测试是一个设计挑战。除了尽量减少测试应用时间(包括粘接前测试和粘接后测试)外,还应考虑到每层测试垫的数量。在本文中,我们提出了一种整数线性规划(ILP)方法来执行三维集成电路测试调度。与之前的工作不同,我们的目标是最小化测试应用时间和所需测试垫数量的加权总和。实验结果一致表明,该方法在实际应用中效果良好。
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3D IC test scheduling with test pads considered
As the design complexity increases, three-dimensional (3D) integrated circuit (IC) design has become an industry trend. However, the testing of a 3D IC is a design challenge. In addition to minimize the test application time (including pre-bond testing and post-bond testing), the number of test pads of each layer should also be taken into account. In this paper, we propose an integer linear programming (ILP) approach to perform the 3D IC test scheduling with test pads considered. Different from those previous works, our objective is to minimize the weighted sum of the test application time and the number of required test pads. Experimental results consistently show that our approach works well in practice.
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