Ki-Hyun Jang, T. Saraya, M. Kobayashi, N. Sawamoto, A. Ogura, T. Hiramoto
{"title":"宽度为10nm的栅极全能多晶硅纳米线晶体管的特性变异性","authors":"Ki-Hyun Jang, T. Saraya, M. Kobayashi, N. Sawamoto, A. Ogura, T. Hiramoto","doi":"10.23919/SNW.2017.8242283","DOIUrl":null,"url":null,"abstract":"The polycrystalline silicon (poly-Si) gate-all-around (GAA) nanowire transistors with 10nm scale width were fabricated under precise width control. The nanowire width is 10nm scale. Measured characteristics show smaller threshold voltage and drain current variability than that of previously reported poly-Si nanowire transistors.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Characterictics variability of gate-all-around polycrystalline silicon nanowire transistors with width of 10nm scale\",\"authors\":\"Ki-Hyun Jang, T. Saraya, M. Kobayashi, N. Sawamoto, A. Ogura, T. Hiramoto\",\"doi\":\"10.23919/SNW.2017.8242283\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The polycrystalline silicon (poly-Si) gate-all-around (GAA) nanowire transistors with 10nm scale width were fabricated under precise width control. The nanowire width is 10nm scale. Measured characteristics show smaller threshold voltage and drain current variability than that of previously reported poly-Si nanowire transistors.\",\"PeriodicalId\":424135,\"journal\":{\"name\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/SNW.2017.8242283\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2017.8242283","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characterictics variability of gate-all-around polycrystalline silicon nanowire transistors with width of 10nm scale
The polycrystalline silicon (poly-Si) gate-all-around (GAA) nanowire transistors with 10nm scale width were fabricated under precise width control. The nanowire width is 10nm scale. Measured characteristics show smaller threshold voltage and drain current variability than that of previously reported poly-Si nanowire transistors.