采用双回路控制的90nA静态电流1.5V-5V 50mA异步折叠LDO

Jun Liu, Troy Bryant, N. Maghari, Jeffery Morroni
{"title":"采用双回路控制的90nA静态电流1.5V-5V 50mA异步折叠LDO","authors":"Jun Liu, Troy Bryant, N. Maghari, Jeffery Morroni","doi":"10.1109/ASSCC.2016.7844175","DOIUrl":null,"url":null,"abstract":"This paper presents a 90 nA quiescent current 1.5V–5.0V LDO regulator in a 0.35 um BiCMOS process. A new dual-loop (asynchronous digital loop and an analog loop) LDO is proposed. The digital loop (D-Loop) boosts the loop response speed under fast switching clock frequencies and the analog loop (Α-Loop) provides a clean output voltage with an ultra-low current consumption. The prototype IC achieves 90 nA of quiescent current during steady state with a power supply of up to 5.0 V. It has a drop-out voltage of 200 mV and a 50 mA output current capability. This prototype is implemented using a 0.35 um BiCMOS process and the active chip area is 0.25 mm2.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 90nA quiescent current 1.5V–5V 50mA asynchronous folding LDO using dual loop control\",\"authors\":\"Jun Liu, Troy Bryant, N. Maghari, Jeffery Morroni\",\"doi\":\"10.1109/ASSCC.2016.7844175\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 90 nA quiescent current 1.5V–5.0V LDO regulator in a 0.35 um BiCMOS process. A new dual-loop (asynchronous digital loop and an analog loop) LDO is proposed. The digital loop (D-Loop) boosts the loop response speed under fast switching clock frequencies and the analog loop (Α-Loop) provides a clean output voltage with an ultra-low current consumption. The prototype IC achieves 90 nA of quiescent current during steady state with a power supply of up to 5.0 V. It has a drop-out voltage of 200 mV and a 50 mA output current capability. This prototype is implemented using a 0.35 um BiCMOS process and the active chip area is 0.25 mm2.\",\"PeriodicalId\":278002,\"journal\":{\"name\":\"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2016.7844175\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2016.7844175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

本文提出了一种基于0.35 um BiCMOS工艺的90 nA静态电流1.5V-5.0V LDO稳压器。提出了一种新的双环(异步数字环和模拟环)LDO。数字环路(D-Loop)在快速开关时钟频率下提高环路响应速度,模拟环路(Α-Loop)提供干净的输出电压和超低的电流消耗。在高达5.0 V的电源下,原型IC在稳定状态下实现了90na的静态电流。它具有200毫伏的降压和50毫安的输出电流能力。该原型采用0.35 um BiCMOS工艺实现,有源芯片面积为0.25 mm2。
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A 90nA quiescent current 1.5V–5V 50mA asynchronous folding LDO using dual loop control
This paper presents a 90 nA quiescent current 1.5V–5.0V LDO regulator in a 0.35 um BiCMOS process. A new dual-loop (asynchronous digital loop and an analog loop) LDO is proposed. The digital loop (D-Loop) boosts the loop response speed under fast switching clock frequencies and the analog loop (Α-Loop) provides a clean output voltage with an ultra-low current consumption. The prototype IC achieves 90 nA of quiescent current during steady state with a power supply of up to 5.0 V. It has a drop-out voltage of 200 mV and a 50 mA output current capability. This prototype is implemented using a 0.35 um BiCMOS process and the active chip area is 0.25 mm2.
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