Performance Prediction of Stacked Nanowire Transistors in the Presence of Random Discrete Dopants and Metal Gate Granularity

Gate-all-around nanowire field effect transistors (GAA-NW-FETs) in a horizontal configuration is now being considered as a strong candidate to extend today's CMOS technology to its ultimate scaling limits. In this paper, full 3-D device simulations are performed to study the effect of random discrete dopants (RDD) and metal gate granularity (MGG) on the performance of a 10nm channel length vertically stacked silicon nanowire FETs. The impact of metal grain crystallographic orientation on the gate work function and presence of discrete dopants on transistor threshold voltage is reported. The discrete dopants have been distributed randomly in the source/drain and channel regions of the device. Due to the small dimensions of the transistor a quantum transport formalism has been deployed in simulation. Our results show the magnitude and importance of RDD and MGG and the need for process optimization to minimize device parameter variations in sub-10nm technology nodes.