EE6: "How Can Hardware Designers Reclaim the Spotlight?"

With the end of Moore’s Law and Dennard Scaling, domain-specific architecture remains the only viable path to continue scaling computing performance. In this era of domain-specific hardware, differentiation will come primarily from efficient hardware design and hardware designers, and the system level will play a key role. Domain specific hardware achieves its performance from massive parallelism, specialized data types and operations, fine-grained memory systems, and efficient interconnection networks. The latter two, memory and interconnect, are domain independent and will be provided by general-purpose platforms, such as GPUs. Hardware system designers will differentiate their products via algorithm-hardware co-design, and the design of special purpose units that provide the data-type and operation specialization – like the TensorCores and RTCores in a Turing GPU. hardware and software accelerate demanding applications, including machine learning, bioinformatics, and logical designing innovative and efficient experimental computing systems. microprocessor hardware MOSSIM Simulation and the Torus wormhole routing and virtual-channel flow control. J-Machine and the M-Machine, experimental parallel computer systems the separation of mechanisms from programming models and very low overhead synchronization and communication mechanisms. the Imagine processor, the concepts of stream processing and partitioned register organizations, the Merrimac supercomputer, to GPU computing, and the ELM low-power processor. National Academy Engineering productivity has not kept pace with Moore’s Law, leading to prohibitive increases in development costs and team sizes for leading edge SoCs. The main strategy for managing complexity in today’s SoCs is through design reuse of proprietary licensed intellectual property (IP) modules. The current IP reuse approach has markedly improved productivity, but the single layer point-to-point approach has limited the scope of reuse and abstraction. A pathway to revolutionizing SoC design is to copy the software design community, where open source has enabled a deep software hierarchy with many abstraction layers, significantly increasing productivity. Open source technology forms the foundation of fields like machine learning that are moving forward at an astounding rate. The adoption of an open source culture within the circuit design community would speed up the circuit innovation cycle, while democratizing access to specialized circuits needed to create state-of-the-art mixed-signal systems. Andreas Olofsson is DARPA the Microsystems Technology Office. His include intelligent design automation, system optimization, and open hardware. Prior to his at DARPA, Mr. Olofsson 20 to designing and testing low-power processors and mixed-signal circuits at Texas Instruments, Analog Devices, and Adapteva. Chip products designed by Mr. Olofsson include low-power digital signal processors (DSPs), charge-coupled device (CCD) readout circuits, and massively parallel reduced instruction set computing (RISC) processors. From 2008 to 2016, Mr. Olofsson the CEO of Adapteva, where he the Epiphany architecture and Parallella open-source computer. The Parallella democratized access to parallel computing and catalyzed the of a community of 10,000 developers and 200 across the globe. Mr. Olofsson in and Electrical and in Electrical Engineering the University of Pennsylvania. Mr. Olofsson is a Member of the IEEE and holds nine U.S. patents.