集成电路封装中电源引脚电流分布的测量

J. Weaver, M. Horowitz
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引用次数: 9

摘要

在现代高性能芯片和系统设计中,保持低电源阻抗是一项关键任务,这取决于电流在芯片、封装和电路板配电层上的流动方式。使用前面描述的简单电感拾取环路,我们通过工作中的大型VLSI芯片的电流测量每个引脚。有趣的是,整个封装的交流电流变化只有33%。这表明对于这个芯片,电流拥挤不是问题。此外,我们还测量了电路板旁路电容电流,并发现电容器提供了它们连接的引脚的峰值瞬态电流的80%n和120%之间。由于最大电流仅略大于连接引脚所需的电流,因此电路板旁路电容主要影响它所连接的引脚,而不会真正绕过该区域的其他VDD引脚。
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Measurement of Supply Pin Current Distributions in Integrated Circuit Packages
Maintaining low supply impedance is a critical task in modern high-performance chip and system design, and this depends on how the current flows on the chip, package, and board power distribution layers. Using a simple inductive pickup loop previously described, we measure the per-pin via currents for a large VLSI chip in operation. Interestingly, the variation in AC current across the package was only 33%. indicating that for this chip current crowding was not an issue. Furthermore, we measured the board bypass capacitance currents as well, and found that the capacitors supplied between 80%n and 120% of the peak transient currents of the pins to which I hey were connected. Since the maximum current is only slightly larger than the current required by the attached pin, the board bypass capacitance primarily affects the pin it is connected to, and does not really bypass the other VDD pins in that region.
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