{"title":"低功耗顺序存取存储器设计","authors":"J. Moon, W. Athas, P. Beerel, J. Draper","doi":"10.1109/CICC.2002.1012778","DOIUrl":null,"url":null,"abstract":"This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16/spl times/16-b SAM and one 64/spl times/16-b SAM (consisting of four 16/spl times/16-b banks) has been designed, fabricated, and evaluated using a 0.25-/spl mu/m CMOS process. With a clock frequency of 40 MHz at 1.2 V, the measured worst-case read power dissipations for the 16/spl times/16-b SAM and the 64/spl times/16-b SAM are 344 /spl mu/W and 358 /spl mu/W respectively, demonstrating power dissipation that is largely independent of SAM size.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Low-power sequential access memory design\",\"authors\":\"J. Moon, W. Athas, P. Beerel, J. Draper\",\"doi\":\"10.1109/CICC.2002.1012778\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16/spl times/16-b SAM and one 64/spl times/16-b SAM (consisting of four 16/spl times/16-b banks) has been designed, fabricated, and evaluated using a 0.25-/spl mu/m CMOS process. With a clock frequency of 40 MHz at 1.2 V, the measured worst-case read power dissipations for the 16/spl times/16-b SAM and the 64/spl times/16-b SAM are 344 /spl mu/W and 358 /spl mu/W respectively, demonstrating power dissipation that is largely independent of SAM size.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012778\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012778","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16/spl times/16-b SAM and one 64/spl times/16-b SAM (consisting of four 16/spl times/16-b banks) has been designed, fabricated, and evaluated using a 0.25-/spl mu/m CMOS process. With a clock frequency of 40 MHz at 1.2 V, the measured worst-case read power dissipations for the 16/spl times/16-b SAM and the 64/spl times/16-b SAM are 344 /spl mu/W and 358 /spl mu/W respectively, demonstrating power dissipation that is largely independent of SAM size.
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