{"title":"精确的自由运行周期合成器(FRPS),具有过程和温度补偿","authors":"B. Pontikakis, F. Boyer, Y. Savaria, H. Bui","doi":"10.1109/MWSCAS.2007.4488754","DOIUrl":null,"url":null,"abstract":"This paper proposes an all-digital, automated, clock generator based on a free-running oscillator that can generate arbitrarily precise frequencies. The entire system can be implemented using standard cells and even has a compensation system to mitigate the effects of environmental variations on frequency. The design is implemented in VHDL and synthesized using Artisan standard-cells in TSMC's 180 nm CMOS technology. Post-layout timing analysis shows that the proposed free-running period synthesizer (FPRS) can operate at a frequency of up to 175 MHz. The architecture was also validated with an implementation on a Xilinx's Spartan 3 FPGA that works at 80 MHz. In both implementations, the worst case peak to peak jitter of the output clock is equal to one period of the free-running oscillator.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"303 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Precise free-running period synthesizer (FRPS) with process and temperature compensation\",\"authors\":\"B. Pontikakis, F. Boyer, Y. Savaria, H. Bui\",\"doi\":\"10.1109/MWSCAS.2007.4488754\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an all-digital, automated, clock generator based on a free-running oscillator that can generate arbitrarily precise frequencies. The entire system can be implemented using standard cells and even has a compensation system to mitigate the effects of environmental variations on frequency. The design is implemented in VHDL and synthesized using Artisan standard-cells in TSMC's 180 nm CMOS technology. Post-layout timing analysis shows that the proposed free-running period synthesizer (FPRS) can operate at a frequency of up to 175 MHz. The architecture was also validated with an implementation on a Xilinx's Spartan 3 FPGA that works at 80 MHz. In both implementations, the worst case peak to peak jitter of the output clock is equal to one period of the free-running oscillator.\",\"PeriodicalId\":256061,\"journal\":{\"name\":\"2007 50th Midwest Symposium on Circuits and Systems\",\"volume\":\"303 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 50th Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2007.4488754\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 50th Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2007.4488754","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Precise free-running period synthesizer (FRPS) with process and temperature compensation
This paper proposes an all-digital, automated, clock generator based on a free-running oscillator that can generate arbitrarily precise frequencies. The entire system can be implemented using standard cells and even has a compensation system to mitigate the effects of environmental variations on frequency. The design is implemented in VHDL and synthesized using Artisan standard-cells in TSMC's 180 nm CMOS technology. Post-layout timing analysis shows that the proposed free-running period synthesizer (FPRS) can operate at a frequency of up to 175 MHz. The architecture was also validated with an implementation on a Xilinx's Spartan 3 FPGA that works at 80 MHz. In both implementations, the worst case peak to peak jitter of the output clock is equal to one period of the free-running oscillator.