{"title":"55纳米CMOS技术的AB类运算放大器","authors":"Paweł Pieńczuk, W. Pleskacz, Mateusz Teodorowski","doi":"10.23919/MIXDES52406.2021.9497543","DOIUrl":null,"url":null,"abstract":"A class AB operational amplifier, designed in UMC CMOS 55 nm technology, is presented. A folded-cascode architecture with a inverter output buffer was implemented. Post- layout corners and Monte Carlo simulations ensure the minimum bandwidth equal to 2 MHz and DC gain equal to 85 dB. Phase margin with a minimum of 67° ensures the stability of the circuit. CMRR and PSRR of at least 85.9 dB and 62.5 dB, respectively, allow the operational amplifier to be used in the majority of applications. The static current consumption does not exceed 25 μA. The die dimensions are 85 μm x 67 μm.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Class AB Operational Amplifier in CMOS 55 nm Technology\",\"authors\":\"Paweł Pieńczuk, W. Pleskacz, Mateusz Teodorowski\",\"doi\":\"10.23919/MIXDES52406.2021.9497543\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A class AB operational amplifier, designed in UMC CMOS 55 nm technology, is presented. A folded-cascode architecture with a inverter output buffer was implemented. Post- layout corners and Monte Carlo simulations ensure the minimum bandwidth equal to 2 MHz and DC gain equal to 85 dB. Phase margin with a minimum of 67° ensures the stability of the circuit. CMRR and PSRR of at least 85.9 dB and 62.5 dB, respectively, allow the operational amplifier to be used in the majority of applications. The static current consumption does not exceed 25 μA. The die dimensions are 85 μm x 67 μm.\",\"PeriodicalId\":375541,\"journal\":{\"name\":\"2021 28th International Conference on Mixed Design of Integrated Circuits and System\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 28th International Conference on Mixed Design of Integrated Circuits and System\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/MIXDES52406.2021.9497543\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/MIXDES52406.2021.9497543","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Class AB Operational Amplifier in CMOS 55 nm Technology
A class AB operational amplifier, designed in UMC CMOS 55 nm technology, is presented. A folded-cascode architecture with a inverter output buffer was implemented. Post- layout corners and Monte Carlo simulations ensure the minimum bandwidth equal to 2 MHz and DC gain equal to 85 dB. Phase margin with a minimum of 67° ensures the stability of the circuit. CMRR and PSRR of at least 85.9 dB and 62.5 dB, respectively, allow the operational amplifier to be used in the majority of applications. The static current consumption does not exceed 25 μA. The die dimensions are 85 μm x 67 μm.
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