{"title":"减少3D-TLC NAND闪存的不可靠页面错误，数据开销减少40%，数据保留时间增加5.0倍","authors":"Kyosuke Maeda, Kyoji Mizoguchi, K. Takeuchi","doi":"10.23919/SNW.2019.8782930","DOIUrl":null,"url":null,"abstract":"This paper proposes Less Reliable Page Error Reduction (LRPER) to achieve both high reliability and small data overhead of 3D-TLC NAND flash memories. LRPER suppresses both lateral charge migration and vertical charge de-trap without redundant reading of memory cells, thus achieving fast write. In addition, data overhead is small by adding flag bits to the highly reliable page. As a result, the data-retention lifetime increases by 5.0-times. The proposal can be implemented in the SSD controller for highly reliable 3D-NAND flash.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"68 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data Overhead Reduction by 40% and Data-retention Time Increase by 5.0x\",\"authors\":\"Kyosuke Maeda, Kyoji Mizoguchi, K. Takeuchi\",\"doi\":\"10.23919/SNW.2019.8782930\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes Less Reliable Page Error Reduction (LRPER) to achieve both high reliability and small data overhead of 3D-TLC NAND flash memories. LRPER suppresses both lateral charge migration and vertical charge de-trap without redundant reading of memory cells, thus achieving fast write. In addition, data overhead is small by adding flag bits to the highly reliable page. As a result, the data-retention lifetime increases by 5.0-times. The proposal can be implemented in the SSD controller for highly reliable 3D-NAND flash.\",\"PeriodicalId\":170513,\"journal\":{\"name\":\"2019 Silicon Nanoelectronics Workshop (SNW)\",\"volume\":\"68 6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/SNW.2019.8782930\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2019.8782930","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data Overhead Reduction by 40% and Data-retention Time Increase by 5.0x
This paper proposes Less Reliable Page Error Reduction (LRPER) to achieve both high reliability and small data overhead of 3D-TLC NAND flash memories. LRPER suppresses both lateral charge migration and vertical charge de-trap without redundant reading of memory cells, thus achieving fast write. In addition, data overhead is small by adding flag bits to the highly reliable page. As a result, the data-retention lifetime increases by 5.0-times. The proposal can be implemented in the SSD controller for highly reliable 3D-NAND flash.
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