Pub Date : 2019-06-09DOI: 10.23919/SNW.2019.8782925
M. Razanoelina, H. Firdaus, Yasuo Takahashi, A. Fujiwara, Y. Ono
The electron nano-aspirator, which we have recently proposed and demonstrated, is a Si device with a T-shaped branch, and can enhance the MOS-transistor current by utilizing the hydrodynamic nature of electrons. Here, we present an investigation on the controllability of the device characteristics and discuss the performance improvement for the future development of low power circuits based on the electron hydrodynamics.
{"title":"Si Electron Nano-Aspirator towards Emerging Hydro-Electronics","authors":"M. Razanoelina, H. Firdaus, Yasuo Takahashi, A. Fujiwara, Y. Ono","doi":"10.23919/SNW.2019.8782925","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782925","url":null,"abstract":"The electron nano-aspirator, which we have recently proposed and demonstrated, is a Si device with a T-shaped branch, and can enhance the MOS-transistor current by utilizing the hydrodynamic nature of electrons. Here, we present an investigation on the controllability of the device characteristics and discuss the performance improvement for the future development of low power circuits based on the electron hydrodynamics.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129108893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To understand the charge effects on semiconductor-metal phase transition in monolayer MoTe2, the modulations of phase transition energies with electrons and holes doping are studied by using the first principle calculation. It is found that the charge will make the total energy of the distorted metal phase lower than the semiconductor phase. Also, the barrier of phase transition from the semiconductor phase to the distorted metal phase can be decreased. Our results can well explain the experimentally observed resistance switching in MoTe2 layer, indicating that the charge doping can be an effective approach to control the phase switching in MoTe2 layer.
{"title":"Charge Effects on Semiconductor-Metal Phase Transition in Mono-layer MoTe2","authors":"Jixuan Wu, Xiaolei Ma, Jiezhi Chen, Xiangwei Jiang","doi":"10.23919/SNW.2019.8782941","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782941","url":null,"abstract":"To understand the charge effects on semiconductor-metal phase transition in monolayer MoTe2, the modulations of phase transition energies with electrons and holes doping are studied by using the first principle calculation. It is found that the charge will make the total energy of the distorted metal phase lower than the semiconductor phase. Also, the barrier of phase transition from the semiconductor phase to the distorted metal phase can be decreased. Our results can well explain the experimentally observed resistance switching in MoTe2 layer, indicating that the charge doping can be an effective approach to control the phase switching in MoTe2 layer.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123725308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, nanoribbon field-effect-transistors (FETs) with an ultra-narrow monolayer MoS2 channel are investigated to understand the transverse scaling limitations of MoS2 FETs. It is observed that the bandgap of monolayer nanoribbon MoS2 can be largely affected by the passivation atoms, wherein OH passivation is more effective than H passivation. Then, impacts of passivation atoms on transport characteristics in MoS2 FETs with ultra-narrow MoS2 channel are calculated. Though higher Ion and lower Ioff can be obtained even in narrow MoS2 FETs with O/H passivation, Ioff is hard to be suppressed due to the contribution of edge states. Our results indicate that edge states engineering could be one key point to integrate MoS2 devices into CMOS technology.
{"title":"Atomistic Study of Transport Characteristics in Sub-1nm Ultra-narrow Molybdenum Disulfide (MoS2) Nanoribbon Field Effect Transistors","authors":"Fei Wang, Xiaolei Ma, Jixuan Wu, Jiezhi Chen, Xiangwei Jiang","doi":"10.23919/SNW.2019.8782953","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782953","url":null,"abstract":"In this work, nanoribbon field-effect-transistors (FETs) with an ultra-narrow monolayer MoS<inf>2</inf> channel are investigated to understand the transverse scaling limitations of MoS<inf>2</inf> FETs. It is observed that the bandgap of monolayer nanoribbon MoS<inf>2</inf> can be largely affected by the passivation atoms, wherein OH passivation is more effective than H passivation. Then, impacts of passivation atoms on transport characteristics in MoS<inf>2</inf> FETs with ultra-narrow MoS<inf>2</inf> channel are calculated. Though higher I<inf>on</inf> and lower I<inf>off</inf> can be obtained even in narrow MoS<inf>2</inf> FETs with O/H passivation, I<inf>off</inf> is hard to be suppressed due to the contribution of edge states. Our results indicate that edge states engineering could be one key point to integrate MoS<inf>2</inf> devices into CMOS technology.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128413939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/SNW.2019.8782943
Zih-Tang Lin, V. Hu
In this paper, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on Ferroelectric FinFET (FE-FinFET) with P-type and N-type substrates respectively, compared to FinFET. The trap position dependent RTN amplitude $left(Delta mathbf{I}_{mathrm{d} /} / mathbf{I}_{mathrm{ds}}right)$ along the channel length and fin height directions are examined. For FE-FinFET and FinFET at $mathbf{V}_{mathbf{g s}}$= 0V, N-type substrate with smaller work function lowers the channel conduction band energy near the bottom of fin along the fin height direction. Therefore, the maximum electron current density occurs at the bottom of fin which becomes the most critical position introducing worst RTN amplitude for N-type substrate. However, for FE-FinFET and FinFET with P-type substrate, the worst RTN amplitude occurs at 0.5 fin height position. Therefore, along the fin height direction, the worst RTN amplitude occurs at different position for FE-FinFET/FinFET with N-type and P-type substrates respectively. Our results show that FE-FinFET exhibits smaller RTN amplitude than FinFET due to its smaller trap induced threshold voltage shift $left(Delta mathbf{V}_{mathrm{T}}right)$. Besides, for both FE-FinFET and FinFET, N-type substrate shows smaller RTN amplitude and RTN induced $Delta mathbf{V}_{mathbf{T}}$ variations than P-type substrate. In other words, RTN induced variations can be suppressed by substrate doping optimization for FE-FinFET and FinFET.
{"title":"Reduced RTN Amplitude and Single Trap induced Variation for Ferroelectric FinFET by Substrate Doping Optimization","authors":"Zih-Tang Lin, V. Hu","doi":"10.23919/SNW.2019.8782943","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782943","url":null,"abstract":"In this paper, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on Ferroelectric FinFET (FE-FinFET) with P-type and N-type substrates respectively, compared to FinFET. The trap position dependent RTN amplitude $left(Delta mathbf{I}_{mathrm{d} /} / mathbf{I}_{mathrm{ds}}right)$ along the channel length and fin height directions are examined. For FE-FinFET and FinFET at $mathbf{V}_{mathbf{g s}}$= 0V, N-type substrate with smaller work function lowers the channel conduction band energy near the bottom of fin along the fin height direction. Therefore, the maximum electron current density occurs at the bottom of fin which becomes the most critical position introducing worst RTN amplitude for N-type substrate. However, for FE-FinFET and FinFET with P-type substrate, the worst RTN amplitude occurs at 0.5 fin height position. Therefore, along the fin height direction, the worst RTN amplitude occurs at different position for FE-FinFET/FinFET with N-type and P-type substrates respectively. Our results show that FE-FinFET exhibits smaller RTN amplitude than FinFET due to its smaller trap induced threshold voltage shift $left(Delta mathbf{V}_{mathrm{T}}right)$. Besides, for both FE-FinFET and FinFET, N-type substrate shows smaller RTN amplitude and RTN induced $Delta mathbf{V}_{mathbf{T}}$ variations than P-type substrate. In other words, RTN induced variations can be suppressed by substrate doping optimization for FE-FinFET and FinFET.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126765283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782975
Jaeyeol Park, Hyungcheol Shin
In this paper, we analyzed lateral migration mechanism of holes (LM) in 3D NAND Flash memory during retention operation. Retention characteristics were investigated using Technology Computer-Aided Design (TCAD) simulation and modeled using Weibull cumulative distribution function (WCD). Time-constant $(tau)$ at various temperatures were extracted through the modeled equation. Finally, the activation energy (Ea) of LM was extracted by applying to the Arrhenius equation.
{"title":"Modeling of Lateral Migration Mechanism of Holes in 3D NAND Flash Memory Charge Trap Layer during Retention Operation","authors":"Jaeyeol Park, Hyungcheol Shin","doi":"10.23919/SNW.2019.8782975","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782975","url":null,"abstract":"In this paper, we analyzed lateral migration mechanism of holes (LM) in 3D NAND Flash memory during retention operation. Retention characteristics were investigated using Technology Computer-Aided Design (TCAD) simulation and modeled using Weibull cumulative distribution function (WCD). Time-constant $(tau)$ at various temperatures were extracted through the modeled equation. Finally, the activation energy (Ea) of LM was extracted by applying to the Arrhenius equation.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115135711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782902
W. Chang, N. Okada, H. Asai, K. Fukuda, Mitsuhiro Okada, T. Endo, Y. Miyata, T. Irisawa
High-k dielectrics of Al2O3, HfO2 and ZrO2 have been directly deposited on MoS2 through plasma enhanced atomic layer deposition (PEALD). Among them, PEALD-ZrO2/MoS2 has shown the highest interfacial quality with high dielectric constant and sharp interface, characterized by CV, XPS and TEM measurements. Dual gate CVD-grown MoS2 MOSFETs using PEALD-ZrO2 as a top-gate dielectric has also been demonstrated.
{"title":"Comparative Study of High-k Dielectric on MoS2 Deposited by Plasma Enhanced ALD","authors":"W. Chang, N. Okada, H. Asai, K. Fukuda, Mitsuhiro Okada, T. Endo, Y. Miyata, T. Irisawa","doi":"10.23919/SNW.2019.8782902","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782902","url":null,"abstract":"High-k dielectrics of Al<inf>2</inf>O<inf>3</inf>, HfO<inf>2</inf> and ZrO<inf>2</inf> have been directly deposited on MoS<inf>2</inf> through plasma enhanced atomic layer deposition (PEALD). Among them, PEALD-ZrO<inf>2</inf>/MoS<inf>2</inf> has shown the highest interfacial quality with high dielectric constant and sharp interface, characterized by CV, XPS and TEM measurements. Dual gate CVD-grown MoS<inf>2</inf> MOSFETs using PEALD-ZrO<inf>2</inf> as a top-gate dielectric has also been demonstrated.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126037009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782932
C. McClellan, C. Bailey, I. Datye, A. Gabourie, R. Grady, K. Schauble, S. Vaziri, E. Pop
As traditional device scaling slows down, three-dimensional (3D) integrated circuits (ICs) are needed to continue Moore’s Law advancements. We show that two-dimensional (2D) semiconductors are promising for heterogeneously integrated 3D ICs owing to their atomically thin nature and unique processing, thermal, and device capabilities.
{"title":"3D Heterogeneous Integration with 2D Materials","authors":"C. McClellan, C. Bailey, I. Datye, A. Gabourie, R. Grady, K. Schauble, S. Vaziri, E. Pop","doi":"10.23919/SNW.2019.8782932","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782932","url":null,"abstract":"As traditional device scaling slows down, three-dimensional (3D) integrated circuits (ICs) are needed to continue Moore’s Law advancements. We show that two-dimensional (2D) semiconductors are promising for heterogeneously integrated 3D ICs owing to their atomically thin nature and unique processing, thermal, and device capabilities.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114934394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782942
Yi-chun Lu, V. Hu
The performance of ferroelectric SOI (FE-SOI) analog circuits considering the impact of interface trap charge (Nit) and gate length (Lg) variations are analysed for the first time. For FE-SOI MOSFETs, the discharging time (ts), on resistance (Ron) of switch circuit, and output current (Iout) of current mirror show superior immunity to Nit and Lg variations compared to the SOI counterparts. FE-SOI MOSFETs show significant improvements in discharging time (-78% and -31%) at Vdd=0.4V and 1V compared to SOI MOSFETs due to the negative capacitance induced voltage amplification and higher drive current. Besides, FE-SOI switch circuit exhibits lower Ron and better Ron flatness which suppresses distortion for audio and signal processing applications. FE-SOI current mirror with larger output resistance shows better current matching (smaller Iout/Iref) than SOI one, and comparable mirroring performance compared to the stacked SOI current mirror. Therefore, FE-SOI current mirror can significantly reduce the circuit complexity and area penalty while maintaining adequate mirroring accuracy.
{"title":"Evaluation of Analog Circuit Performance for Ferroelectric SOI MOSFETs considering Interface Trap Charges and Gate Length Variations","authors":"Yi-chun Lu, V. Hu","doi":"10.23919/SNW.2019.8782942","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782942","url":null,"abstract":"The performance of ferroelectric SOI (FE-SOI) analog circuits considering the impact of interface trap charge (N<inf>it</inf>) and gate length (L<inf>g</inf>) variations are analysed for the first time. For FE-SOI MOSFETs, the discharging time (t<inf>s</inf>), on resistance (R<inf>on</inf>) of switch circuit, and output current (I<inf>out</inf>) of current mirror show superior immunity to N<inf>it</inf> and L<inf>g</inf> variations compared to the SOI counterparts. FE-SOI MOSFETs show significant improvements in discharging time (-78% and -31%) at V<inf>dd</inf>=0.4V and 1V compared to SOI MOSFETs due to the negative capacitance induced voltage amplification and higher drive current. Besides, FE-SOI switch circuit exhibits lower R<inf>on</inf> and better R<inf>on</inf> flatness which suppresses distortion for audio and signal processing applications. FE-SOI current mirror with larger output resistance shows better current matching (smaller I<inf>out</inf>/I<inf>ref</inf>) than SOI one, and comparable mirroring performance compared to the stacked SOI current mirror. Therefore, FE-SOI current mirror can significantly reduce the circuit complexity and area penalty while maintaining adequate mirroring accuracy.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129746296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782900
T. Mizutani, K. Takeuchi, T. Saraya, M. Kobayashi, T. Hiramoto
Extreme value theory was applied to the estimation of worst case SRAM data retention voltage (DRV). It was found that the worst case DRV follows Gumbel distributions, and can be estimated by measuring not all, but only the worst case DRV of several SRAM arrays.
{"title":"Application of Extreme Value Theory to Statistical Analyses of Worst Case SRAM Data Retention Voltage","authors":"T. Mizutani, K. Takeuchi, T. Saraya, M. Kobayashi, T. Hiramoto","doi":"10.23919/SNW.2019.8782900","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782900","url":null,"abstract":"Extreme value theory was applied to the estimation of worst case SRAM data retention voltage (DRV). It was found that the worst case DRV follows Gumbel distributions, and can be estimated by measuring not all, but only the worst case DRV of several SRAM arrays.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121544316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：