{"title":"一种完全可合成的双dco频率跟踪注入锁相环","authors":"Xuanchi Yu, Yan Chen, Gaofena Jin, Fei Feng, Xun Luo, Xiang Gao","doi":"10.1109/ICTA56932.2022.9962990","DOIUrl":null,"url":null,"abstract":"This paper presents a fully synthesizable injection locked phase-locked loop (PLL), with a dual-DCO frequency tracking. The design has been fabricated in 55-nm CMOS and the layout is realized completely by digital flows. The proposed PLL covers a 0.2-to-1.2-GHz tuning range, achieving an absolute rms jitter (integrated from 100kHz to 100MHz) of 3.2ps at 4.3-mW power consumption, with a corresponding jitter-power figure of merit (FoM) of -224dB and the occupied core area is only 0.0225 mm2.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS\",\"authors\":\"Xuanchi Yu, Yan Chen, Gaofena Jin, Fei Feng, Xun Luo, Xiang Gao\",\"doi\":\"10.1109/ICTA56932.2022.9962990\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a fully synthesizable injection locked phase-locked loop (PLL), with a dual-DCO frequency tracking. The design has been fabricated in 55-nm CMOS and the layout is realized completely by digital flows. The proposed PLL covers a 0.2-to-1.2-GHz tuning range, achieving an absolute rms jitter (integrated from 100kHz to 100MHz) of 3.2ps at 4.3-mW power consumption, with a corresponding jitter-power figure of merit (FoM) of -224dB and the occupied core area is only 0.0225 mm2.\",\"PeriodicalId\":325602,\"journal\":{\"name\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"197 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICTA56932.2022.9962990\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9962990","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS
This paper presents a fully synthesizable injection locked phase-locked loop (PLL), with a dual-DCO frequency tracking. The design has been fabricated in 55-nm CMOS and the layout is realized completely by digital flows. The proposed PLL covers a 0.2-to-1.2-GHz tuning range, achieving an absolute rms jitter (integrated from 100kHz to 100MHz) of 3.2ps at 4.3-mW power consumption, with a corresponding jitter-power figure of merit (FoM) of -224dB and the occupied core area is only 0.0225 mm2.
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