{"title":"聚焦搜索法提高组合电路测试构建效率的实验研究","authors":"V. Kulikov, V. V. Mokhor","doi":"10.1109/EWDTS.2011.6116588","DOIUrl":null,"url":null,"abstract":"Consider the possibility reducing the iteration value in building complete validation tests for digital devices. Building a test for a given fault is reduced to searching the terminal node in the signals assignment tree. The reducing is achieved by accumulating and using of information about dead-end conditions to avoid similar situations in the earlier stages. Allows any faults that can be described by logical functions.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"On experimental research of efficiency of tests construction for combinational circuits by the focused search method\",\"authors\":\"V. Kulikov, V. V. Mokhor\",\"doi\":\"10.1109/EWDTS.2011.6116588\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Consider the possibility reducing the iteration value in building complete validation tests for digital devices. Building a test for a given fault is reduced to searching the terminal node in the signals assignment tree. The reducing is achieved by accumulating and using of information about dead-end conditions to avoid similar situations in the earlier stages. Allows any faults that can be described by logical functions.\",\"PeriodicalId\":339676,\"journal\":{\"name\":\"2011 9th East-West Design & Test Symposium (EWDTS)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-09-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 9th East-West Design & Test Symposium (EWDTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2011.6116588\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 9th East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2011.6116588","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On experimental research of efficiency of tests construction for combinational circuits by the focused search method
Consider the possibility reducing the iteration value in building complete validation tests for digital devices. Building a test for a given fault is reduced to searching the terminal node in the signals assignment tree. The reducing is achieved by accumulating and using of information about dead-end conditions to avoid similar situations in the earlier stages. Allows any faults that can be described by logical functions.
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