/spl times/pipesCompiler:一个在芯片上实例化应用特定网络的工具

A. Jalabert, S. Murali, L. Benini, G. Micheli
{"title":"/spl times/pipesCompiler:一个在芯片上实例化应用特定网络的工具","authors":"A. Jalabert, S. Murali, L. Benini, G. Micheli","doi":"10.1109/DATE.2004.1268999","DOIUrl":null,"url":null,"abstract":"Future systems on chips (SoCs) will integrate a large number of processor and storage cores onto a single chip and require networks on chip (NoC) to support the heavy communication demands of the system. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication infrastructure should optimally match communication patterns among these components accounting for the individual component needs. In this paper we present /spl times/pipesCompiler, a tool for automatically instantiating an application-specific NoC for heterogeneous multi-processor SoCs. The /spl times/pipesCompiler instantiates a network of building blocks from a library of composable soft macros (switches, network interfaces and links) described in SystemC at the cycle-accurate level. The network components are optimized for that particular network and support reliable, latency-insensitive operation. Example systems with application-specific NoCs built using the /spl times/pipesCompiler show large savings in area (factor of 6.5), power (factor of 2.4) and latency (factor of 1.42) when compared to a general-purpose mesh-based NoC architecture.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"243","resultStr":"{\"title\":\"/spl times/pipesCompiler: a tool for instantiating application specific networks on chip\",\"authors\":\"A. Jalabert, S. Murali, L. Benini, G. Micheli\",\"doi\":\"10.1109/DATE.2004.1268999\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Future systems on chips (SoCs) will integrate a large number of processor and storage cores onto a single chip and require networks on chip (NoC) to support the heavy communication demands of the system. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication infrastructure should optimally match communication patterns among these components accounting for the individual component needs. In this paper we present /spl times/pipesCompiler, a tool for automatically instantiating an application-specific NoC for heterogeneous multi-processor SoCs. The /spl times/pipesCompiler instantiates a network of building blocks from a library of composable soft macros (switches, network interfaces and links) described in SystemC at the cycle-accurate level. The network components are optimized for that particular network and support reliable, latency-insensitive operation. Example systems with application-specific NoCs built using the /spl times/pipesCompiler show large savings in area (factor of 6.5), power (factor of 2.4) and latency (factor of 1.42) when compared to a general-purpose mesh-based NoC architecture.\",\"PeriodicalId\":335658,\"journal\":{\"name\":\"Proceedings Design, Automation and Test in Europe Conference and Exhibition\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-02-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"243\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Design, Automation and Test in Europe Conference and Exhibition\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DATE.2004.1268999\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DATE.2004.1268999","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 243

摘要

未来的片上系统(soc)将把大量的处理器和存储核心集成到单个芯片上,并且需要片上网络(NoC)来支持系统的繁重通信需求。soc的各个组件本质上是异构的,具有广泛不同的功能和通信需求。通信基础设施应该最优地匹配这些组件之间的通信模式,以满足各个组件的需求。在本文中,我们介绍了/spl times/pipesCompiler,这是一个为异构多处理器soc自动实例化特定于应用程序的NoC的工具。/spl times/pipesCompiler从SystemC中描述的可组合软宏(开关、网络接口和链接)库中实例化一个构建块网络,在周期精确级别上进行描述。网络组件针对特定的网络进行了优化,并支持可靠的、对延迟不敏感的操作。与基于网格的通用NoC架构相比,使用/spl times/pipesCompiler构建的具有特定应用程序NoC的示例系统在面积(6.5倍)、功耗(2.4倍)和延迟(1.42倍)方面节省了很多。
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/spl times/pipesCompiler: a tool for instantiating application specific networks on chip
Future systems on chips (SoCs) will integrate a large number of processor and storage cores onto a single chip and require networks on chip (NoC) to support the heavy communication demands of the system. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication infrastructure should optimally match communication patterns among these components accounting for the individual component needs. In this paper we present /spl times/pipesCompiler, a tool for automatically instantiating an application-specific NoC for heterogeneous multi-processor SoCs. The /spl times/pipesCompiler instantiates a network of building blocks from a library of composable soft macros (switches, network interfaces and links) described in SystemC at the cycle-accurate level. The network components are optimized for that particular network and support reliable, latency-insensitive operation. Example systems with application-specific NoCs built using the /spl times/pipesCompiler show large savings in area (factor of 6.5), power (factor of 2.4) and latency (factor of 1.42) when compared to a general-purpose mesh-based NoC architecture.
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