Fabrication of vertical InAs-Si heterojunction tunnel field effect transistors

Gated p-i-n diodes operating as tunnel field effect transistors (TFETs) [1] are recently attracting much attention because of potential benefits over conventional MOSFETs. They are expected to have lower off-current, and operate at lower supply voltage compared to MOSFETs. Unfortunately, these promises are very difficult to realize using materials like Si, Ge and its alloys. However, encouraging experimental results were recently obtained using lower bandgap III–V (InGaAs) material systems [2, 3] offering higher tunneling probabilities. Here we report first results on the fabrication and electrical characterization of III–V / Si heterojunction TFETs with InAs as low bandgap source. This material combination maintains the advantages of Si as channel, drain and substrate material as proposed in [4].