{"title":"利用金属有机分解制备的SrTiO/ sub3 /缓冲层控制铁电PbTiO/ sub3 /薄膜的结构","authors":"H. Fukuda, K. Kimura, K. Salam, S. Nomura","doi":"10.1109/ISAF.2002.1195891","DOIUrl":null,"url":null,"abstract":"Polycrystalline PbTiO/sub 3/ thin films were successfully formed on SrTiO/sub 3/ buffer layer by metalorganic decomposition (MOD) technique. The PbTiO/sub 3/ films showed the perovskite structure after annealing at 700/spl deg/C for 30 min in N/sub 2/ ambient. A higher dielectric constant of 157 is obtained in the PbTiO/sub 3//SrTiO/sub 3//Si structure. The hysteresis loop in the capacitance-voltage curves of the MFIS configuration indicated a memory window of 1.2 V with a programming voltage swing of /spl plusmn/5 V due to polarization effect. The memory window will satisfy the practical application of the MFIS-FET memories operating at low voltage in future ULSIs.","PeriodicalId":415725,"journal":{"name":"Proceedings of the 13th IEEE International Symposium on Applications of Ferroelectrics, 2002. ISAF 2002.","volume":"546 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Structure control of ferroelectric PbTiO/sub 3/ thin films using SrTiO/sub 3/ buffer layer prepared by metalorganic decomposition\",\"authors\":\"H. Fukuda, K. Kimura, K. Salam, S. Nomura\",\"doi\":\"10.1109/ISAF.2002.1195891\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Polycrystalline PbTiO/sub 3/ thin films were successfully formed on SrTiO/sub 3/ buffer layer by metalorganic decomposition (MOD) technique. The PbTiO/sub 3/ films showed the perovskite structure after annealing at 700/spl deg/C for 30 min in N/sub 2/ ambient. A higher dielectric constant of 157 is obtained in the PbTiO/sub 3//SrTiO/sub 3//Si structure. The hysteresis loop in the capacitance-voltage curves of the MFIS configuration indicated a memory window of 1.2 V with a programming voltage swing of /spl plusmn/5 V due to polarization effect. The memory window will satisfy the practical application of the MFIS-FET memories operating at low voltage in future ULSIs.\",\"PeriodicalId\":415725,\"journal\":{\"name\":\"Proceedings of the 13th IEEE International Symposium on Applications of Ferroelectrics, 2002. ISAF 2002.\",\"volume\":\"546 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-05-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 13th IEEE International Symposium on Applications of Ferroelectrics, 2002. ISAF 2002.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISAF.2002.1195891\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 13th IEEE International Symposium on Applications of Ferroelectrics, 2002. ISAF 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISAF.2002.1195891","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Structure control of ferroelectric PbTiO/sub 3/ thin films using SrTiO/sub 3/ buffer layer prepared by metalorganic decomposition
Polycrystalline PbTiO/sub 3/ thin films were successfully formed on SrTiO/sub 3/ buffer layer by metalorganic decomposition (MOD) technique. The PbTiO/sub 3/ films showed the perovskite structure after annealing at 700/spl deg/C for 30 min in N/sub 2/ ambient. A higher dielectric constant of 157 is obtained in the PbTiO/sub 3//SrTiO/sub 3//Si structure. The hysteresis loop in the capacitance-voltage curves of the MFIS configuration indicated a memory window of 1.2 V with a programming voltage swing of /spl plusmn/5 V due to polarization effect. The memory window will satisfy the practical application of the MFIS-FET memories operating at low voltage in future ULSIs.
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