大型机系统的CPU和缓存的逻辑综合与验证

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC Pub Date : 1994-02-28 DOI:10.1109/EDTC.1994.326898

H. Nguyen, J. Tual, L. Ducousso, M. Thill, P. Vallet

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引用次数: 4

摘要

本文描述了利用BONSAI系统大规模应用逻辑综合和形式化验证技术来设计一个高端大型机系统的CPU和缓存。该应用程序的主要特点是集成了一套逻辑合成和形式化验证技术的方法，以构建有效的逻辑设计系统，以支持高性能，高密度电路的设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Logic synthesis and verification of the CPU and caches of a mainframe system

This paper describes the large scale application of logic synthesis and formal verification using the BONSAI system to the design of the CPU and caches of a high-end mainframe system. The key feature of this application is the methodology that integrates a set of logic synthesis and formal verification techniques to build an effective logic-design system to support the design of high-performance, high-density circuits.<>

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Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC

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