Model and FPGA Implementation of Pseudorandom Sequence Generators Based on Invertible Matrices

This paper considers a pseudo-random sequence generator in form of a autonomous automaton with the output function. A model of the automaton output function is proposed, which is defined based on a set of invertible matrices, with the capacity relevant to the maximum number of the bijective transformations of two binary variables over the GF(2) field. In the model proposed, there is an algorithmic possibility to modify the structure of pseudo-random sequences read on the automaton output, as related to the input M-sequence within the period equal to 2n-1, n > 1. The output function of a given automaton allows obtaining an assembly of output sequences, which is defined by the lower estimate written as O(22n). Based on the model proposed, a pseudo-random sequence generator hardware implementation is presented, with the period of 2n-1, n = 256, in the FPGA basis, using the Xilinx ISE WebPACK 14.7 CAD software product. Hardware complexity estimates of the generator are presented, as well. It is shown that the hardware complexity relating to the pseudo-random sequence generator implementation, which are represented in the FPGA XC3 S700A basis, increase linearly with the increase of n.