In-Situ Characterization of High-Speed I/O Chip-Package Systems

This paper reports methods of signal integrity model validation for high-speed I/O chip-package systems including simultaneous switching noise, package power/ground noise and crosstalk. IBIS-models of I/O chip performance are extracted from measurements using high impedance probes. IBIS macro model based SPICE simulations and onboard measurements are compared to optimize package model over a several GHz range. A characterization IC including differential CMOS current-mode logic, (CML) and single-ended, Gunning transceiver logic, (GTL) I/O were designed with TI 65 nm digital CMOS processes. Key CMOS CML characterization data is used to investigate the effects of the package on signal integrity performance and GTL data will be forthcoming.