{"title":"一种确定单双栅无结晶体管耗尽宽度的方法","authors":"Kaushik Chandra Deva Sarma, Santanu Sharma","doi":"10.1109/EDCAV.2015.7060550","DOIUrl":null,"url":null,"abstract":"This paper presents a method for determining the depletion width of single and double gate Junction Less transistor. By solving 1D Poisson's equation the depletion width expression is obtained. The variation of depletion width for both n-channel and p-channel device with doping concentration, gate voltage, drain to source voltage and dielectric constant of gate dielectric are shown.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A method for determination of depletion width of single and double gate junction less transistor\",\"authors\":\"Kaushik Chandra Deva Sarma, Santanu Sharma\",\"doi\":\"10.1109/EDCAV.2015.7060550\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a method for determining the depletion width of single and double gate Junction Less transistor. By solving 1D Poisson's equation the depletion width expression is obtained. The variation of depletion width for both n-channel and p-channel device with doping concentration, gate voltage, drain to source voltage and dielectric constant of gate dielectric are shown.\",\"PeriodicalId\":277103,\"journal\":{\"name\":\"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)\",\"volume\":\"109 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDCAV.2015.7060550\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDCAV.2015.7060550","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A method for determination of depletion width of single and double gate junction less transistor
This paper presents a method for determining the depletion width of single and double gate Junction Less transistor. By solving 1D Poisson's equation the depletion width expression is obtained. The variation of depletion width for both n-channel and p-channel device with doping concentration, gate voltage, drain to source voltage and dielectric constant of gate dielectric are shown.