集成电路时钟的测试方案

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI:10.1109/EDTC.1997.582398

M. Favalli, C. Metra

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引用次数: 5

摘要

提出了一种检测数字同步集成电路内部时钟信号异常偏差的测试方案。该方案基于一种新型CMOS传感电路，其紧凑性和可测试性使其适用于离线和在线测试。

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Testing scheme for IC's clocks

This paper proposes a testing scheme to detect abnormal skews between clock signals inside digital synchronous ICs. The scheme is based on a new CMOS sensing circuit whose compactness and testability with respect to a large set of failures make it suitable for both off-line and on-line testing.

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Proceedings European Design and Test Conference. ED & TC 97

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