一个自校准12b12 µs CMOS ADC

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156622

Hae-Sung Lee, D. Hodges, P. Gray

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引用次数: 5

摘要

利用一种简单的数字算法对加权电容ADC的线性误差进行了校正。在500ns内分辨率为50μV的CMOS比较器允许这种方法在22us内产生12b的精确转换。芯片面积小于7mm2。

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A self calibrating 12b 12µs CMOS ADC

Linearity errors of a weighted-capacitor ADC have been corrected, using a simple digital algorithm. A CMOS comparator which resolves 50μV in 500ns, allows this approach to yield a 12b accurate conversion in 22us. Chip area is under 7mm2.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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