具有柱状通道结构的门控晶闸管DRAM单元

2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI:10.23919/SNW.2017.8242302

Hyungjin Kim, M. Kwon, Myung-Hyun Baek, Sungmin Hwang, Sihyun Kim, Taejin Jang, Jeong-Jun Lee, Hyun-Min Kim, Kitae Lee, Byung-Gook Park

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引用次数: 0

摘要

本文提出了一种基于柱状通道和侧壁栅极的门控晶闸管的DRAM单元，并对其进行了器件仿真研究。在基区存储的电子使读电流降低电位势垒的差异。由于其基于热注入的机制，具有10ns以下的快速写入速度和自连接字线的高可扩展性结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Gated-thyristor DRAM cell with pillar channel structure

In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word line.

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2017 Silicon Nanoelectronics Workshop (SNW)

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