采用0.12 /spl mu/m STI工艺技术的1.8 V 1gb NAND闪存

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992121

J. Lee, Heung-Soo Im, D. Byeon, Kyeong-Han Lee, Dong-Hyuk Chae, Kyongjoo Lee, Y. Lim, Jungdal Choi, Young-Il Seo, Jong-Sik Lee, K. Suh

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引用次数: 3

摘要

1.8 V 1gb闪存采用0.12 /spl mu/m STI工艺技术。电荷泵工作在<1.8 V。通过应用32单元NAND结构，在一个块间距内数字化放置在中心的行解码器。包含两个锁存器的页缓冲区支持一个缓存程序，可将程序速度提高到7 MB/s。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1.8 V 1 Gb NAND flash memory with 0.12 /spl mu/m STI process technology

A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at <1.8 V. A center-placed row decoder is digitized in one block pitch by applying a 32-cell NAND structure. A page buffer, containing two latches, supports a cache-program to improve program speed to 7 MB/s.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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