Kyunghwan Kim, Kangseop Lee, Seung-Uk Choi, Ji-Seong Kim, Chan-Gyu Choi, Ho-Jin Song
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A 97–107 GHz Triple-Stacked-FET Power Amplifier with 23.7dB Peak Gain, 15.1dBm PSAT, and 18.6% PAEMAX in 28-nm FD-SOI CMOS
A 97–107 GHz power amplifier (PA) based on a stacked-FET topology is presented. In a triple-stacked-FeT structure, stacking efficiency is analyzed using four combinations of series or shunt inductors for compensating phase of impedances between stack nodes, and optimal inductances are chosen. Phase-compensation inductors are implemented by considering a finite quality factor with the tradeoff between layout size and stacking efficiency. A layout of a transistor cell is customized to reduce gate resistance. The triple-stacked-FET PA provides peak PSAT and PAEMAX of 15.1 dBm and 18.6%, respectively. The presented PA achieves the highest power density and efficiency compared to state-of-the-art CMOS PAs in F-band.
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