Fast Electrostatic Analysis For VLSI Aging based on Generative Learning

Electrostatic analysis, which computes electrical potential and electrical field, is important for VLSI reliability and high speed circuit design. Deep learning provides new opportunities and challenges to speedup the analysis process by learning physical laws and feature representations. In this work, we propose an image generative learning framework for electrostatic analysis for VLSI dielectric aging estimation. This work leverages the observation that the synthesized multi layer interconnect VLSI layout can be viewed as layered 2D images and the analysis can be viewed as the image generation. The efficient image-to-image translation property of generative learning is therefore used to obtain the potential distribution on the respective interconnect layers. Compared with the recent CNN-based electrostatic analysis method, the new method can lead to 1.54x speedup for inference due to reduced neural network structures and parameters. We demonstrate the proposed method for time-dependent dielectric breakdown analysis and show the significant speedup compared to the traditional numerical method.