通过硅孔(TSV)扇贝平滑技术

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC) Pub Date : 2014-12-01 DOI:10.1109/EPTC.2014.7028274

Goon Heng Wong, K. Chui, G. Lau, W. Loh, Lian Hongyu

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引用次数: 2

摘要

为了以小尺寸实现高性能，并通过在微芯片上实现更多晶体管来克服摩尔定律，可以通过2.5D和3D芯片堆叠[1]。透硅通孔(TSV)是2.5 D和3D技术的关键，越来越受到许多大型芯片制造商的关注[2]。硅在TSV中蚀刻过程中，由于蚀刻机理的影响，会形成各种缺陷[3]。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Through silicon via (TSV) scallop smoothening technique

To achieve high performance in a small form factor and to overcome Moore Law's by still achieving more transistors on microchips are through 2.5D and 3D chips stacking [1]. Through Si via (TSV) is the key to 2.5 D and 3D technology and is gaining more and more interest from many giant chipmakers [2]. Various defects may form during silicon etch in TSV due to the etching mechanism [3].

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2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

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