{"title":"具有自调节GRO TDC和dco专用稳压器的高psrr ADPLL","authors":"Yanfeng Li, Yutao Liu, W. Rhee, Zhihua Wang","doi":"10.1109/VLSI-DAT.2015.7114499","DOIUrl":null,"url":null,"abstract":"This paper describes a PSRR enhancing method for the all-digital phase-locked loop (ADPLL) by utilizing a self-regulated gated ring-oscillator (SR-GRO) time-to-digital converter (TDC) and a voltage regulator just for a digitally-controlled oscillator (DCO). The SR-GRO employs a replica supply noise monitoring circuit which tracks supply noise and enables feed-forward error cancellation over broad spectrum. A prototype ADPLL implemented in 65nm CMOS achieves >25dB PSRR when 100mVpp 1MHz supply noise is injected to both the TDC and the DCO. Experimental results show that the SR-GRO TDC can also suppress the supply coupling induced phase noise.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"59 S1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator\",\"authors\":\"Yanfeng Li, Yutao Liu, W. Rhee, Zhihua Wang\",\"doi\":\"10.1109/VLSI-DAT.2015.7114499\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a PSRR enhancing method for the all-digital phase-locked loop (ADPLL) by utilizing a self-regulated gated ring-oscillator (SR-GRO) time-to-digital converter (TDC) and a voltage regulator just for a digitally-controlled oscillator (DCO). The SR-GRO employs a replica supply noise monitoring circuit which tracks supply noise and enables feed-forward error cancellation over broad spectrum. A prototype ADPLL implemented in 65nm CMOS achieves >25dB PSRR when 100mVpp 1MHz supply noise is injected to both the TDC and the DCO. Experimental results show that the SR-GRO TDC can also suppress the supply coupling induced phase noise.\",\"PeriodicalId\":369130,\"journal\":{\"name\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"volume\":\"59 S1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT.2015.7114499\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114499","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator
This paper describes a PSRR enhancing method for the all-digital phase-locked loop (ADPLL) by utilizing a self-regulated gated ring-oscillator (SR-GRO) time-to-digital converter (TDC) and a voltage regulator just for a digitally-controlled oscillator (DCO). The SR-GRO employs a replica supply noise monitoring circuit which tracks supply noise and enables feed-forward error cancellation over broad spectrum. A prototype ADPLL implemented in 65nm CMOS achieves >25dB PSRR when 100mVpp 1MHz supply noise is injected to both the TDC and the DCO. Experimental results show that the SR-GRO TDC can also suppress the supply coupling induced phase noise.
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