首次演示两个金属级半大马士革互连与完全自对准过孔在18MP

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830150

G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. T. Le, O. Pedreira, A. Lesniewska, G. Martinez-Alanis, S. Park, Z. Tokei

{"title":"首次演示两个金属级半大马士革互连与完全自对准过孔在18MP","authors":"G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. T. Le, O. Pedreira, A. Lesniewska, G. Martinez-Alanis, S. Park, Z. Tokei","doi":"10.1109/vlsitechnologyandcir46769.2022.9830150","DOIUrl":null,"url":null,"abstract":"In this paper we demonstrate the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects from 26 to 18nm metal pitch (MP), fabricated on 300mm wafers. We have developed a novel integration flow, using the principle of subtractive etching of Ru, on 2 subsequent metal levels. Using structures with programmed overlay shift, we demonstrate the functionality of a fully self-aligned via process which results in working devices with placement errors of up to 5nm. Furthermore, we show via-to-line breakdown field > 9MV/cm, confirming FSAV.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP\",\"authors\":\"G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. T. Le, O. Pedreira, A. Lesniewska, G. Martinez-Alanis, S. Park, Z. Tokei\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830150\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we demonstrate the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects from 26 to 18nm metal pitch (MP), fabricated on 300mm wafers. We have developed a novel integration flow, using the principle of subtractive etching of Ru, on 2 subsequent metal levels. Using structures with programmed overlay shift, we demonstrate the functionality of a fully self-aligned via process which results in working devices with placement errors of up to 5nm. Furthermore, we show via-to-line breakdown field > 9MV/cm, confirming FSAV.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830150\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830150","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

在本文中，我们展示了半damascene集成方案的功能，该方案具有完全自对准过孔(FSAV)，用于在300mm晶圆上制造的26至18nm金属间距(MP)的互连。我们开发了一种新的集成流程，使用Ru的减法蚀刻原理，在2个随后的金属水平上。使用具有编程覆盖移位的结构，我们展示了完全自对准的通孔工艺的功能，其结果是工作器件的放置误差高达5nm。此外，我们显示过线击穿场> 9MV/cm，证实了FSAV。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP

In this paper we demonstrate the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects from 26 to 18nm metal pitch (MP), fabricated on 300mm wafers. We have developed a novel integration flow, using the principle of subtractive etching of Ru, on 2 subsequent metal levels. Using structures with programmed overlay shift, we demonstrate the functionality of a fully self-aligned via process which results in working devices with placement errors of up to 5nm. Furthermore, we show via-to-line breakdown field > 9MV/cm, confirming FSAV.

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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