{"title":"用于亚微米多电平互连建模的参数化SPICE子电路","authors":"Keh-Jeng Chang, S. Oh, N. Chang, K. Lee","doi":"10.1109/VLSIT.1992.200653","DOIUrl":null,"url":null,"abstract":"A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"458 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Parameterized SPICE subcircuits for submicron multilevel interconnect modeling\",\"authors\":\"Keh-Jeng Chang, S. Oh, N. Chang, K. Lee\",\"doi\":\"10.1109/VLSIT.1992.200653\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"458 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200653\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parameterized SPICE subcircuits for submicron multilevel interconnect modeling
A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.<>
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