动态可编程逻辑阵列的串扰测试图生成

J. Liu, W. Jone, S.R. Das
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引用次数: 0

摘要

在现代深亚微米(DSM)电路中,信号串扰可能出现在两根长长的平行导线之间。动态可编程逻辑阵列(PLAs)可能遭受串扰噪声,这将导致电路由于电荷损失而故障。本文根据聚乳酸动态串扰噪声的特点,提出了一种自动测试模式生成(ATPG)方法来检测各生产线的最大串扰噪声。仿真MCNC - PLA基准电路的实验结果证明了该算法的有效性
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Crosstalk Test Pattern Generation for Dynamic Programmable Logic Arrays
In modern deep sub-micron (DSM) circuits, signal crosstalk can arise between two long parallel wires. Dynamic programmable logic arrays (PLAs) may suffer crosstalk noises that will cause the circuit to malfunction due to charge loss. In this paper, based on the characteristics of dynamic PLA crosstalk noises, we present an automatic test pattern generation (ATPG) method to detect the maximum crosstalk noise for each product line. Experimental results obtained by simulating MCNC PLA benchmark circuits demonstrate the efficiency of the ATPG and method
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