Comparative Analysis of Hardware Implementations of a Convolutional Neural Network

Artificial Neural Networks (ANNs) have become the most popular machine learning technique for data processing, performing central functions in a wide variety of applications. In many cases, these models are used within constrained scenarios, in which a local execution of the algorithm is necessary to avoid latency and safety issues of remote computing (e.g, autonomous vehicles, edge devices in IoT networks). Even so, the known computational complexity of these models is still a challenge in such contexts, as implementation costs and performance requirements are difficult to balance. In these scenarios, pa-rameter quantization techniques are essential to simplifying the operations and memory footprint to make the hardware implementation more viable. In this paper, a case study is devised in which a convolutional neural network (CNN) architecture is fully implemented in hardware with three different optimization strategies, having parameters mapped to low bit-width fixed point integers with a power-of-two quantization scheme. Both ASIC and FPGA implementation flows are followed, allowing for an in-depth analysis of each circuit version. The obtained results show that the adopted quantization process enables optimizations on the implemented circuit, reducing about 50% of the circuitry area and 87.5% of the memory requirement. At the same time, the application performance was kept at the same level.