{"title":"GaAs异质结双极1K栅极阵列","authors":"Hen Yuan, W. Mclevige, Hung Shih, A. Hearn","doi":"10.1109/ISSCC.1984.1156638","DOIUrl":null,"url":null,"abstract":"This report will discuss the design, fabrication and performance of a 1K heterojunction I2L gate array with a base bar size of 3.55 × 3.80mm2, containing 1024 internal gates, 64 programmable I/O buffers and 8 pads for the power supply. For general circuit applications the layout provides 300 global wire channels: 150 each in the horizontal and vertical directions.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"37 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"GaAs heterojunction bipolar 1K gate array\",\"authors\":\"Hen Yuan, W. Mclevige, Hung Shih, A. Hearn\",\"doi\":\"10.1109/ISSCC.1984.1156638\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This report will discuss the design, fabrication and performance of a 1K heterojunction I2L gate array with a base bar size of 3.55 × 3.80mm2, containing 1024 internal gates, 64 programmable I/O buffers and 8 pads for the power supply. For general circuit applications the layout provides 300 global wire channels: 150 each in the horizontal and vertical directions.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"37 6\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156638\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156638","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This report will discuss the design, fabrication and performance of a 1K heterojunction I2L gate array with a base bar size of 3.55 × 3.80mm2, containing 1024 internal gates, 64 programmable I/O buffers and 8 pads for the power supply. For general circuit applications the layout provides 300 global wire channels: 150 each in the horizontal and vertical directions.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
