一款0.18/spl mu/m CMOS全集成6.25Gbps单干扰多速率串扰消除IC，适用于传统背板和互连应用

Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2004-05-09 DOI:10.1109/SPI.2004.1409009

F. Bien, A. Raghavan, Z. Nami, C. Lee, A. Kim, M. Vrazel, E. Gebara, S. Bajekal, B. Schmukler, J. Laskar

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引用次数: 4

摘要

本文演示了一种多速率串扰消除器，用于主动消除背板信道环境中由单个干扰源引起的近端串扰。拟议的IC在更高的数据速率下增强了现有传统背板的性能，从而避免了升级到更高端的背板和连接器的相关成本。该集成电路已在0.18/spl μ m CMOS工艺中制造，原型测试台证明了在高达6.25Gbps的数据速率下将误码率(BER)性能提高超过5个数量级的能力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 0.18/spl mu/m CMOS fully integrated 6.25Gbps single aggressor multi-rate crosstalk cancellation IC for legacy backplane and interconnect applications

A multi-rate crosstalk canceller for active cancellation of near end cross talk (NEXT) caused by a single aggressor in a backplane channel environment has been demonstrated in this paper. The proposed IC enhances the performance of existing legacy backplane at higher data rates, thereby avoiding the costs associated with upgrading to higher end backplanes and connectors. The IC has been fabricated in a 0.18/spl mu/m CMOS process and the prototype test bench demonstrated capability of improving the bit-error rate (BER) performance in excess of 5 orders of magnitude at data rates up to 6.25Gbps.

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Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects

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