Fully ion implanted 4096-bit high speed DSA MOS RAM

DIFFUSION-SELF-ALIGNED (DM) M O S I C ~ ' , or D M O S ~ have received attention as subnanosecond and high density devices. In this paper, the experimental results of a DSA MOS memory fabricated by full ion implantation techniques to achieve better threshold voltage controllability will be dcscribed. Access time is 60 ns; power consumed is 950mW. Figure 1 shows cross section of the DSA E-D inverter. It is apparent from the figure, that the effective channel region of the DSA transistor is determined by the diffusion length difference between boron and arsenic layer. All dopants were deposited by ion implantatio-n method on P(71) Si substrate; resistivity was 100 "200 Q-cm, crystal orientation (loo), respectively. The threshold voltage of the device was controlled within 1.20 ? 0.15V and the effective channel length was 0.4 pm. The gain factor was 5 times larger than that of the conventional NMOS3. Features of the DSA MOS process are: 1 ) E-D gate achieved by N-channel 71 planar technique; 2 ) selective oxidation process (SOP) adapted to obtain high packing density and to reduce surface steps; 3) Si gate also used for a smaller feedback capacitance and higher packing density; and 4) all dopants deposited by ion implantation method to improve control of threshold voltage. To evaluate the basic electrical characteristics of these devices, 1 9 stag: ring oscillators have been fabricated by varing process parameters. Figure 2 shows the propagation delay time versus power dissipation, where the parameters were varied for the amount of channel dope to the depletion FET and power supply voltages. In the unhatched region, the driving capability of the DSA MOS FET is smaller than that of the load FET, thus the inverter does not operate. The minimum power delay product (0.05 pJ) and the minimum propagation delay time (0.32 ns) are shown in the ploy. Using this process, a 4096-bit fully decoded dynamic R/W random access memory was developed (Figure 3) using a 5 p m minimum as a base. The memory cell uses a 1 Tr/cell structure to avoid Vth to minimize inverse connection effects due to high __