N. Weste, M. Bickerstaff, T. Arivoli, P. Ryan, J. Dalton, D. Skellern, T. Percival
{"title":"用于WLAN应用的50 MHz 16点FFT处理器","authors":"N. Weste, M. Bickerstaff, T. Arivoli, P. Ryan, J. Dalton, D. Skellern, T. Percival","doi":"10.1109/CICC.1997.606666","DOIUrl":null,"url":null,"abstract":"This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 /spl mu/m TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"37 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A 50 MHz 16-point FFT processor for WLAN applications\",\"authors\":\"N. Weste, M. Bickerstaff, T. Arivoli, P. Ryan, J. Dalton, D. Skellern, T. Percival\",\"doi\":\"10.1109/CICC.1997.606666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 /spl mu/m TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.\",\"PeriodicalId\":111737,\"journal\":{\"name\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"volume\":\"37 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1997.606666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 50 MHz 16-point FFT processor for WLAN applications
This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 /spl mu/m TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
