{"title":"流水线体系结构合成中的自动操作员配置","authors":"K. N. McNall, A. Casavant","doi":"10.1109/DAC.1990.114850","DOIUrl":null,"url":null,"abstract":"An algorithm is presented for automating the choice of operator configurations while synthesizing a pipelined design. The chosen configuration set must meet the design constraints of the pipeline (number of stages and stage time) while minimizing the total cost(s) (e.g., area, power) of the design. The configuration algorithm is first used with heuristics to make initial operator choices for insertion of stage latches and then to choose optimally configurations within each stage. The new algorithm allows the designer to specify the number of stages in the pipeline as well as the clocking frequency of each stage. It also permits the use of totally arbitrary timing functions-that is, an implementation may produce different output times if the ready times of its various inputs are rearranged.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Automatic operator configuration in the synthesis of pipelined architectures\",\"authors\":\"K. N. McNall, A. Casavant\",\"doi\":\"10.1109/DAC.1990.114850\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An algorithm is presented for automating the choice of operator configurations while synthesizing a pipelined design. The chosen configuration set must meet the design constraints of the pipeline (number of stages and stage time) while minimizing the total cost(s) (e.g., area, power) of the design. The configuration algorithm is first used with heuristics to make initial operator choices for insertion of stage latches and then to choose optimally configurations within each stage. The new algorithm allows the designer to specify the number of stages in the pipeline as well as the clocking frequency of each stage. It also permits the use of totally arbitrary timing functions-that is, an implementation may produce different output times if the ready times of its various inputs are rearranged.<<ETX>>\",\"PeriodicalId\":118552,\"journal\":{\"name\":\"27th ACM/IEEE Design Automation Conference\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th ACM/IEEE Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1990.114850\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1990.114850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automatic operator configuration in the synthesis of pipelined architectures
An algorithm is presented for automating the choice of operator configurations while synthesizing a pipelined design. The chosen configuration set must meet the design constraints of the pipeline (number of stages and stage time) while minimizing the total cost(s) (e.g., area, power) of the design. The configuration algorithm is first used with heuristics to make initial operator choices for insertion of stage latches and then to choose optimally configurations within each stage. The new algorithm allows the designer to specify the number of stages in the pipeline as well as the clocking frequency of each stage. It also permits the use of totally arbitrary timing functions-that is, an implementation may produce different output times if the ready times of its various inputs are rearranged.<>