A 10-Bit 10-Ms/S 5.72 nW Mixed SAR Logic for ADC Used in Wireless Sensor Node

This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to digital converter (ADC)used in the wireless sensor node (WSN). A SAR is either synchronous or mixed mode logic, and it has a ring counter and output register. A proposed mixed mode logic is to partitioning the design into synchronous logic each having its own clock and data with asynchronous logic is exchanged asynchronously using handshake signals. This combination allows it to decrease the power and making it faster. The proposed low power SAR logic circuits are designed and simulated using TSMC 0.18 $m$ CMOS technology. Synchronous and mixed mode SAR logic achieves power of 6.35 nW and 5.72 nW respectively at 1 $V$.