{"title":"一种0.18um CMOS制程的紧凑SPDT开关，具有高线性度和低插入损耗","authors":"M. Teshiba, G. Sakamoto, T. Cisco","doi":"10.1109/CSICS07.2007.36","DOIUrl":null,"url":null,"abstract":"A compact CMOS SPDT switch fabricated in 0.18 mum BiCMOS technology has been successfully demonstrated at X-Ku-band. The fully integrated chip exhibits a low insertion loss of 1.9 dB and an isolation of 22.5 dB at 17 GHz. By reverse biasing the source/drain (S/D) diode junctions, the switch achieves a PldB of 21 dBm and TOI greater than 30 dB in a very compact structure. The small footprint, along with the performance being comparable to GaAs switches, makes the switch a very attractive, low cost building block circuit for MMIC designs.","PeriodicalId":370697,"journal":{"name":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A Compact SPDT Switch in 0.18um CMOS Process With High Linearity and Low Insertion Loss\",\"authors\":\"M. Teshiba, G. Sakamoto, T. Cisco\",\"doi\":\"10.1109/CSICS07.2007.36\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A compact CMOS SPDT switch fabricated in 0.18 mum BiCMOS technology has been successfully demonstrated at X-Ku-band. The fully integrated chip exhibits a low insertion loss of 1.9 dB and an isolation of 22.5 dB at 17 GHz. By reverse biasing the source/drain (S/D) diode junctions, the switch achieves a PldB of 21 dBm and TOI greater than 30 dB in a very compact structure. The small footprint, along with the performance being comparable to GaAs switches, makes the switch a very attractive, low cost building block circuit for MMIC designs.\",\"PeriodicalId\":370697,\"journal\":{\"name\":\"2007 IEEE Compound Semiconductor Integrated Circuits Symposium\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Compound Semiconductor Integrated Circuits Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS07.2007.36\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Compound Semiconductor Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS07.2007.36","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Compact SPDT Switch in 0.18um CMOS Process With High Linearity and Low Insertion Loss
A compact CMOS SPDT switch fabricated in 0.18 mum BiCMOS technology has been successfully demonstrated at X-Ku-band. The fully integrated chip exhibits a low insertion loss of 1.9 dB and an isolation of 22.5 dB at 17 GHz. By reverse biasing the source/drain (S/D) diode junctions, the switch achieves a PldB of 21 dBm and TOI greater than 30 dB in a very compact structure. The small footprint, along with the performance being comparable to GaAs switches, makes the switch a very attractive, low cost building block circuit for MMIC designs.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
