Venkata S. Rayudu, Ki Yong Kim, D. Pan, R. Gharpurey
{"title":"一种输入节点谐波响应减小的基于反馈的n径接收机","authors":"Venkata S. Rayudu, Ki Yong Kim, D. Pan, R. Gharpurey","doi":"10.1109/RFIC54546.2022.9863091","DOIUrl":null,"url":null,"abstract":"A downconversion receiver employing a switch-based N-path filter with reduced input harmonic response and harmonic translation from around the $3^{\\text{rd}}$ and the $5^{\\text{th}}$ LO harmonics is presented. The N-path filter employs 8 paths, and is embedded inside a harmonic-selective negative feedback loop. A pulse-width-modulated LO (PWM-LO) is used in the feedback upconverter to reduce the noise injected around the LO fundamental at the input of the N-path downconverter. The architecture is verified in a 65-nm CMOS technology. Approximately 15–18 dB reduction in the $3\\mathrm{f}_{LO}$ and $5\\mathrm{f}_{LO}$ harmonic response, and 8–10 dB enhancement in harmonic-blocker 3-dB compression is observed in measurement. The use of a PWM-LO, instead of a rectangular clock in the upconverter, improves noise figure by nearly 4 dB.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Feedback-Based N-Path Receiver with Reduced Input-Node Harmonic Response\",\"authors\":\"Venkata S. Rayudu, Ki Yong Kim, D. Pan, R. Gharpurey\",\"doi\":\"10.1109/RFIC54546.2022.9863091\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A downconversion receiver employing a switch-based N-path filter with reduced input harmonic response and harmonic translation from around the $3^{\\\\text{rd}}$ and the $5^{\\\\text{th}}$ LO harmonics is presented. The N-path filter employs 8 paths, and is embedded inside a harmonic-selective negative feedback loop. A pulse-width-modulated LO (PWM-LO) is used in the feedback upconverter to reduce the noise injected around the LO fundamental at the input of the N-path downconverter. The architecture is verified in a 65-nm CMOS technology. Approximately 15–18 dB reduction in the $3\\\\mathrm{f}_{LO}$ and $5\\\\mathrm{f}_{LO}$ harmonic response, and 8–10 dB enhancement in harmonic-blocker 3-dB compression is observed in measurement. The use of a PWM-LO, instead of a rectangular clock in the upconverter, improves noise figure by nearly 4 dB.\",\"PeriodicalId\":415294,\"journal\":{\"name\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC54546.2022.9863091\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC54546.2022.9863091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Feedback-Based N-Path Receiver with Reduced Input-Node Harmonic Response
A downconversion receiver employing a switch-based N-path filter with reduced input harmonic response and harmonic translation from around the $3^{\text{rd}}$ and the $5^{\text{th}}$ LO harmonics is presented. The N-path filter employs 8 paths, and is embedded inside a harmonic-selective negative feedback loop. A pulse-width-modulated LO (PWM-LO) is used in the feedback upconverter to reduce the noise injected around the LO fundamental at the input of the N-path downconverter. The architecture is verified in a 65-nm CMOS technology. Approximately 15–18 dB reduction in the $3\mathrm{f}_{LO}$ and $5\mathrm{f}_{LO}$ harmonic response, and 8–10 dB enhancement in harmonic-blocker 3-dB compression is observed in measurement. The use of a PWM-LO, instead of a rectangular clock in the upconverter, improves noise figure by nearly 4 dB.