{"title":"温度敏感性节点间距在ASTAP有限差分模型的平帽单和多芯片模块","authors":"K.J. Arbeitman","doi":"10.1109/STHERM.1993.225328","DOIUrl":null,"url":null,"abstract":"Examines the sensitivity of ASTAP (Advanced Statistical Analysis Program) chip temperatures to model mesh size (node spacing) for flat cap single- and multichip modules and develops guidelines for mesh size selection which ensure a certain level of model accuracy without wasting resources with unnecessary model complication. Temperature output from models generated with the ASTAP model preprocessor (AMP) are first verified against the results from a finite-element modeling package. ASTAP chip temperatures as a function of node spacing are plotted. Optimum node spacing is determined as being where chip temperature variability decreases below the order of a user-defined value for all chips on a module. Guidelines are recommended for the most efficient mesh size selection as a function of module size, maximum chip power density, and maximum vertical chip attach 1D thermal resistances on the module.<<ETX>>","PeriodicalId":369022,"journal":{"name":"[1993 Proceedings] Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Temperature sensitivity to node spacing in ASTAP finite difference modelling for flat cap single- and multi-chip modules\",\"authors\":\"K.J. Arbeitman\",\"doi\":\"10.1109/STHERM.1993.225328\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Examines the sensitivity of ASTAP (Advanced Statistical Analysis Program) chip temperatures to model mesh size (node spacing) for flat cap single- and multichip modules and develops guidelines for mesh size selection which ensure a certain level of model accuracy without wasting resources with unnecessary model complication. Temperature output from models generated with the ASTAP model preprocessor (AMP) are first verified against the results from a finite-element modeling package. ASTAP chip temperatures as a function of node spacing are plotted. Optimum node spacing is determined as being where chip temperature variability decreases below the order of a user-defined value for all chips on a module. Guidelines are recommended for the most efficient mesh size selection as a function of module size, maximum chip power density, and maximum vertical chip attach 1D thermal resistances on the module.<<ETX>>\",\"PeriodicalId\":369022,\"journal\":{\"name\":\"[1993 Proceedings] Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-02-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1993 Proceedings] Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/STHERM.1993.225328\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993 Proceedings] Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/STHERM.1993.225328","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Temperature sensitivity to node spacing in ASTAP finite difference modelling for flat cap single- and multi-chip modules
Examines the sensitivity of ASTAP (Advanced Statistical Analysis Program) chip temperatures to model mesh size (node spacing) for flat cap single- and multichip modules and develops guidelines for mesh size selection which ensure a certain level of model accuracy without wasting resources with unnecessary model complication. Temperature output from models generated with the ASTAP model preprocessor (AMP) are first verified against the results from a finite-element modeling package. ASTAP chip temperatures as a function of node spacing are plotted. Optimum node spacing is determined as being where chip temperature variability decreases below the order of a user-defined value for all chips on a module. Guidelines are recommended for the most efficient mesh size selection as a function of module size, maximum chip power density, and maximum vertical chip attach 1D thermal resistances on the module.<>