VHDL分析中的挑战

Proceedings EURO-DAC '92: European Design Automation Conference Pub Date : 1992-11-01 DOI:10.1109/EURDAC.1992.246181

David B. Bernstein, Rodney Farrow, David Charness

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摘要

VHSIC硬件描述语言(VHDL)是一种丰富而复杂的形式语言。它的许多构造允许对硬件行为进行广泛的描述。然而，许多特性需要语义，这通常很难或昂贵地正确分析。作者讨论了其中的几个特性，解释了它们存在的原因，它们难以实现的原因，以及一些简化它们使用的策略

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Challenges in the analysis of VHDL

VHSIC hardware description language (VHDL) is a rich and complex formal language. Its many constructs allow for a wide description of hardware behavior. Many of the features, however, require semantics which are often difficult or expensive to properly analyze. The authors discuss several of these features, explaining why they exist, why they are hard to implement, and some strategies for easing their use.<>

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Proceedings EURO-DAC '92: European Design Automation Conference

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