Sub-Threshold Drain Current Model of Shell-Core Architecture Double Gate JunctionLess Transistor

Sub-threshold model for advanced shell doped Double Gate Junctionless transistor has been presented in this work. Electrical parameters such as potential, threshold voltage Vth, leakage current Ioff, sub-threshold slopes SS and Drain Induced Barrier Lowering DIBL are evaluated analytically and compared with the results extracted from ATLAS TCAD software. Different configurations of shell doping have been used in this work such as: high-low-high, low-high-low, low-low-high and uniform. Obtained results shows that high-low-high doping profile of DG-JL transistor suppresses the leakage current more efficiently and also provide good sub-threshold slope and DIBL compared to uniform and other doping profiles. In shell doped DG-JL transistor, additional tuning parameter is present (i.e. the thickness of individual doping layer)which further helps in optimizing the device design for sub-20nm circuits' applications.